Debug control DIP switches. More...

Macros
#define	SCx_DIPSW__C0 0xC0
#define	SCx_DIPSW__C1 0xC1
#define	SCx_DIPSW__C2 0xC2
#define	SCx_DIPSW__C3 0xC3
#define	SCx_DIPSW__C4 0xC4
#define	SCx_DIPSW__C5 0xC5
#define	SCx_DIPSW__C6 0xC6
#define	SCx_DIPSW__C7 0xC7
#define	SCx_DIPSW__C8 0xC8
#define	SCx_DIPSW__C9 0xC9
#define	SCx_DIPSW__CA 0xCA
#define	SCx_DIPSW__CB 0xCB
#define	SCx_DIPSW__CC 0xCC
#define	SCx_DIPSW__CD 0xCD
#define	SCx_DIPSW__CE 0xCE
#define	SCx_DIPSW__CF 0xCF
#define	SCx_DIPSW__D0 0xD0
#define	SCx_DIPSW__D1 0xD1
#define	SCE_DIPSW_ENABLE_TOOL_PHYMEMPART 0xD2
	Enable TOOL physical memory partition.
#define	SCx_DIPSW__D3 0xD3
#define	SCx_DIPSW__D4 0xD4
#define	SCx_DIPSW__D5 0xD5
#define	SCx_DIPSW__D6 0xD6
#define	SCx_DIPSW__D7 0xD7
#define	SCx_DIPSW__D8 0xD8
#define	SCx_DIPSW__D9 0xD9
#define	SCx_DIPSW__DA 0xDA
#define	SCx_DIPSW__DB 0xDB
#define	SCx_DIPSW__DC 0xDC
#define	SCx_DIPSW__DD 0xDD
#define	SCx_DIPSW__DE 0xDE
#define	SCx_DIPSW__DF 0xDF

Detailed Description

Debug control DIP switches.

Macro Definition Documentation

◆ SCE_DIPSW_ENABLE_TOOL_PHYMEMPART

#define SCE_DIPSW_ENABLE_TOOL_PHYMEMPART 0xD2

Enable TOOL physical memory partition.

Requires the SoC to be equipped with additional LPDDR2.

Definition at line 122 of file dipsw.h.

◆ SCx_DIPSW__C0

#define SCx_DIPSW__C0 0xC0

Definition at line 98 of file dipsw.h.

◆ SCx_DIPSW__C1

#define SCx_DIPSW__C1 0xC1

Definition at line 99 of file dipsw.h.

◆ SCx_DIPSW__C2

#define SCx_DIPSW__C2 0xC2

Definition at line 100 of file dipsw.h.

◆ SCx_DIPSW__C3

#define SCx_DIPSW__C3 0xC3

Definition at line 101 of file dipsw.h.

◆ SCx_DIPSW__C4

#define SCx_DIPSW__C4 0xC4

Definition at line 102 of file dipsw.h.

◆ SCx_DIPSW__C5

#define SCx_DIPSW__C5 0xC5

Definition at line 103 of file dipsw.h.

◆ SCx_DIPSW__C6

#define SCx_DIPSW__C6 0xC6

Definition at line 104 of file dipsw.h.

◆ SCx_DIPSW__C7

#define SCx_DIPSW__C7 0xC7

Definition at line 105 of file dipsw.h.

◆ SCx_DIPSW__C8

#define SCx_DIPSW__C8 0xC8

Definition at line 106 of file dipsw.h.

◆ SCx_DIPSW__C9

#define SCx_DIPSW__C9 0xC9

Definition at line 107 of file dipsw.h.

◆ SCx_DIPSW__CA

#define SCx_DIPSW__CA 0xCA

Definition at line 108 of file dipsw.h.

◆ SCx_DIPSW__CB

#define SCx_DIPSW__CB 0xCB

Definition at line 109 of file dipsw.h.

◆ SCx_DIPSW__CC

#define SCx_DIPSW__CC 0xCC

Definition at line 110 of file dipsw.h.

◆ SCx_DIPSW__CD

#define SCx_DIPSW__CD 0xCD

Definition at line 111 of file dipsw.h.

◆ SCx_DIPSW__CE

#define SCx_DIPSW__CE 0xCE

Definition at line 112 of file dipsw.h.

◆ SCx_DIPSW__CF

#define SCx_DIPSW__CF 0xCF

Definition at line 113 of file dipsw.h.

◆ SCx_DIPSW__D0

#define SCx_DIPSW__D0 0xD0

Definition at line 114 of file dipsw.h.

◆ SCx_DIPSW__D1

#define SCx_DIPSW__D1 0xD1

Definition at line 115 of file dipsw.h.

◆ SCx_DIPSW__D3

#define SCx_DIPSW__D3 0xD3

Definition at line 124 of file dipsw.h.

◆ SCx_DIPSW__D4

#define SCx_DIPSW__D4 0xD4

Definition at line 125 of file dipsw.h.

◆ SCx_DIPSW__D5

#define SCx_DIPSW__D5 0xD5

PA (Performance Analysis) RAM selection When 1: 0x0800'0000 bytes at PA 0x7800'0000 When 0: 0x2000'0000 bytes at PA 0x8000'0000

Definition at line 132 of file dipsw.h.

◆ SCx_DIPSW__D6

#define SCx_DIPSW__D6 0xD6

Definition at line 133 of file dipsw.h.

◆ SCx_DIPSW__D7

#define SCx_DIPSW__D7 0xD7

Definition at line 134 of file dipsw.h.

◆ SCx_DIPSW__D8

#define SCx_DIPSW__D8 0xD8

Definition at line 135 of file dipsw.h.

◆ SCx_DIPSW__D9

#define SCx_DIPSW__D9 0xD9

Definition at line 136 of file dipsw.h.

◆ SCx_DIPSW__DA

#define SCx_DIPSW__DA 0xDA

Definition at line 137 of file dipsw.h.

◆ SCx_DIPSW__DB

#define SCx_DIPSW__DB 0xDB

Definition at line 138 of file dipsw.h.

◆ SCx_DIPSW__DC

#define SCx_DIPSW__DC 0xDC

Definition at line 139 of file dipsw.h.

◆ SCx_DIPSW__DD

#define SCx_DIPSW__DD 0xDD

Definition at line 140 of file dipsw.h.

◆ SCx_DIPSW__DE

#define SCx_DIPSW__DE 0xDE

Definition at line 141 of file dipsw.h.

◆ SCx_DIPSW__DF

#define SCx_DIPSW__DF 0xDF

Definition at line 142 of file dipsw.h.

Macros